Command Address (CA) training is a process to optimize the CA bus (Row/Column command bus and CKE) setup and hold times relative to the memory clock. CA training helps the memory controller compensate for signal skew while making sure data input setup and hold timing (as well as command and address input timing) requirements are met. Without proper CA training, the memory can result in such failures as higher bit error rates and destabilize system operations.
In a typical memory system of a computer system, a memory controller facilitates the access of memory modules in the computer system. The memory controller transmits a host of signals to the memories including address signals, control signals, clock signals, etc. to access data from the memories or to send data to the memory. In order to send and receive correct data to and from the memories, the memory controller should train (or modify) CA signals with respect to a clock signal.
Memory controllers use CA training to improve timing margins of the CA bus. Typically, the memory controller trains the CA signals by transmitting a particular CA signal with respect to a clock signal to the memory and then analyzing a response from each memory to ascertain if the memory correctly received the particular CA signal. Upon a successful response from the memory, the memory controller delays the phase of the particular CA signal with respect to the clock signal and then re-transmits the delayed particular CA signal with a delayed phase to the memory. The memory controller then analyzes a response from the memory to ascertain if the memory correctly received the delayed particular CA signal.
High Bandwidth Memory (HBM) is an emerging memory standard defined by the JEDEC organization. HBM is a high-performance dynamic random access memory (DRAM) that uses wide-interface architecture to achieve high-speed and low-power operation. The HBM subsystems involve different types of memory controllers (full-speed, half-speed), HBM PHY (mixed-signal physical interface), and HBM Dynamic Random Access Memory (DRAM). The HBM subsystem is especially suitable for applications involving high performance graphics and computing, high end networking and communication devices, and memory-hungry processors. The HBM may also be fitting to enable systems with extremely high bandwidth requirements like future high-performance GPUs. The HBM standard applies stacked DRAM die and is built using through-silicon vias technologies to support bandwidth from 1 GB/s to 2 GB/s per signal at 400-1000 MHz DDR. HBM achieves such high bandwidth while using less power by stacking up to eight DRAM dies, including an optional base die with a memory controller, which are interconnected by through-silicon vias and microbumps.
The higher HBM speeds require that DRAM channels be carefully tuned for optimal signal quality and DDR bus timing. HBM CA bus signals operate at frequencies (e.g., 1.6 Gbps or 2.0 Gbps) which makes it difficult to satisfy CA bus setup and hold timings. As such, executing CA training before any normal operation becomes necessary to ensure correct timing on CA Bus when HBM works at such high frequencies. With the rise of HBM as the next generation memory technology, there is a need to implement CA training even though HBM protocol does not provide a specific CA training mechanism.
Currently, CA training mechanisms are explicitly defined by mobile double data ram (DDR) protocols, but HBM does not explicitly define a specific mechanism to execute a CA training process. For example, HBM protocol does not define a specific “CA training mode” such as in LPDDR3 and LPDDR4 protocols. Unlike LPDDR3's built in training mechanisms, HBM CA bus signals cannot be mapped to DQ and patterns, which are defined for training on CA bus by LPDDR3 protocol, and cannot be returned via DQ to the HBM controller. Furthermore, HBM protocol does not explicitly ensure that MRS command can be sent correctly to HBM DRAM at any frequency, which is defined by LPDDR4 protocol. As such, the HBM controller cannot ensure that HBM DRAM can be set to a correct mode via MRS without CA training when the frequency is very high. Therefore, the HBM controller cannot implement a CA training process by using similar ways as LPDDR3 or LPDDR4 controllers.
Therefore, there is a need for methods, and a system for initializing and implementing a CA training process for HBM to optimize CA bus setup and hold times.